A high-resolution time interpolator based on a delay locked loop and an RC delay line
نویسندگان
چکیده
منابع مشابه
A High-Resolution Time Interpolator Based on a Delay Locked Loop and an RC Delay Line
An architecture for a time interpolation circuit with an rms error of 25 ps has been developed in a 0.7m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage depend...
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ژورنال
عنوان ژورنال: IEEE Journal of Solid-State Circuits
سال: 1999
ISSN: 0018-9200
DOI: 10.1109/4.792603